1. Field of the Invention
The present invention relates to a voltage regulator including a leakage current control circuit configured to prevent an increase in output voltage caused by a leakage current of an output transistor.
2. Description of the Related Art
FIG. 7 is a circuit diagram illustrating a related-art voltage regulator.
The related-art voltage regulator includes PMOS transistors 103, 104, 106, 108, 111, and 121, NMOS transistors 105, 107, 109, 114, and 122, resistors 112 and 113, capacitors 801 and 802, a reference voltage circuit 131, a constant current circuit 110, a ground terminal 100, a power supply terminal 101, and an output terminal 102.
The PMOS transistors 103, 104, 106, and 108, the NMOS transistors 105, 107, 109, and 114, and the constant current circuit 110 form an error amplifier circuit.
The capacitor 801 directly feeds back an output voltage Vout of the output terminal 102 to the inside of the error amplifier circuit. With this configuration, a zero point fzcp is added in a high frequency region in frequency characteristics of the voltage regulator. Thus, a zero point fzfb can be set on the low frequency side, and hence a sufficient phase margin can be obtained even in a voltage regulator of three-stage amplification. Further, the setting of the zero point fzfb on the low frequency side can improve power supply rejection ratio (PSRR) characteristics as well. When the voltage regulator of three-stage amplification is configured in this way, a low equivalent series resistance (ESR) ceramic capacitor can be used for an output capacitor, to thereby obtain an output voltage Vout with a small ripple (see, for example, FIG. 10 of Japanese Patent Application Laid-open No. 2006-127225).
The related-art voltage regulator, however, has a problem in that, at high temperature and under a light load state in which a small load is connected to the output terminal 102, the output voltage Vout is increased due to a leakage current Ileak from the PMOS transistor 111.